1. Technical Field
The present invention relates to a liquid crystal display device, more particularly, a liquid crystal display device which samples and retains a positive-polarity video signal and a negative-polarity image signal with respect each pixel individually, retains the signals in two retentive capacities and thereafter applies their hold voltages for the signals to a pixel electrode alternately to drive a liquid crystal element in alternating current.
2. Background Arts
In recent years, there is widely used a LCOS (Liquid Crystal on Silicon) type liquid crystal display device as an essential component to project images on a projector unit or a projection-type television. As this LCOS type liquid crystal display device, Japanese Patent Publication Laid-open No. 2009-223289 discloses a liquid crystal display device which has respective pixels arranged in matrix at intersections between multiple pairs of data lines, each pair consisting of two data lines (column signal lines), and multiple gate lines (row scanning lines) and which allows a positive-polarity video signal and a negative-polarity video signal for each pixel to be independently retained as samples in two retentive capacities and thereafter, applies their hold voltages to pixel electrodes alternately to drive liquid crystal elements in AC (alternating current).
FIG. 1 illustrates an exemplary equivalent circuit diagram of one pixel of this liquid crystal display device. In this figure, one pixel 10 comprises two pixel selecting transistors Q1 and Q2 for writing in positive/negative polarity video signals, two independent retentive capacities Cs1 and Cs2 for retaining voltages for these video signals with both polarities in parallel, respective transistors Q3 to Q7 and one liquid crystal element LC. In the example shown in FIG. 1, all the transistors Q1 to Q7 are formed by N-channel field-effect transistors (FET). However, these transistors do not always have to be formed by N-channel field-effect transistors. The liquid crystal element LC has a well-known structure where a liquid crystal layer (displaying body) LCM is interposed between a pixel electrode PE and a common electrode CE opposed to each other. The transistors Q3 and Q7 and the transistors Q4 and Q7 form so-called “source follower buffers”, respectively. The transistors Q3 and Q4 function as signal inputting transistors, while the transistor Q7 functions as a current generator load. The transistor Q7 is arranged on the subsequent stage of the polarity switching transistors Q5 and Q6. Namely, the transistor Q7 is arranged at a node of the pixel electrode PE to serve as a common load for the source follower buffers for two polarities. As the source follower buffers of MOS transistors have almost-infinite input resistances, electrical charges accumulated in the retentive capacities Cs1 and Cs2 are retained without any leakage until signals are newly written after one vertical scanning period.
Further, each pixel includes a positive-polarity data line Di+ and a negative-polarity data line Di− in pairs, which are respectively supplied with video signals of different polarities sampled in a not-shown data-line driving circuit. Respective drain terminals of the pixel selecting transistors Q1 and Q2 are connected to the positive-polarity data line Di+ and the negative-polarity data line Di−, respectively. While, respective gate terminals of the transistors Q1 and Q2 are commonly connected to a row scanning line (gate line) Gj of an identical row.
Next, with reference to the timing charts of FIGS. 2A to 2Q the AC (alternating current) drive control of this pixel 10 will be described in brief. In these figures, FIG. 2A illustrates a vertical synchronizing signal VD, while FIG. 2B illustrates a load-characteristics control signal of the line B, which is applied to a gate of the transistor Q7 in the pixel 10 of FIG. 1. Similarly, FIG. 2C illustrates the waveform of a gate control signal of the line S+, which is applied to a gate of the switching transistor Q5 transferring a positive-polarity drive voltage in the pixel 10, while FIG. 2D illustrates the waveform of a gate control signal of the line S−, which is applied to a gate of the switching transistor Q6 transferring a negative-polarity drive voltage in the pixel 10.
Note that FIG. 3 shows relationships in gray scale between black-level and white-level in positive-polarity and negative-polarity video signals “a”, “b” both written in a pixel. As shown in the figure, the positive-polarity video signal “a” designates black level as the minimum gray scale when the signal level is at a minimum and also designates white level as the maximum gray scale when the signal level is at a maximum. In contrast, the negative-polarity video signal “b” designates white level as the maximum gray scale when the signal level is at a minimum and also designates black level as the minimum gray scale when the signal level is at a maximum. The inversion center of the positive-polarity video signal “a” and the negative-polarity video signal “b” is shown with “c”.
In FIG. 1, while the gate control signal of the line S+ of FIG. 2C is being at a high level, the positive-polarity switching transistor Q5 is turned on. During this period, if the load characteristics control signal supplied to the line B is at a high level as shown in FIG. 2B, then the source follower buffer is activated so that the node of the pixel driving electrode PE is charged at the level of a positive-polarity video signal. Under condition that the potential of the pixel driving electrode PE is charged completely, if the load characteristics control signal of the line B is switched to a low level and the gate control signal of the line S+ is also switched to a low level as well, the pixel driving electrode PE is brought into its floating condition, so that the liquid crystal capacity is maintained with the positive-polarity drive voltage.
On the other hand, while the gate control signal of the line S− of FIG. 2D is being at a high level, the negative-polarity switching transistor Q6 is turned on. During this period, if the load characteristics control signal supplied to the line B is at a high level as shown in FIG. 2B, then the source follower buffer is activated so that the node of the pixel driving electrode PE is charged at the level of the negative-polarity video signal. Under condition that the potential of the pixel driving electrode PE is charged fully, when the load characteristics control signal of the line B is switched to its low level and the gate control signal of the line S− is also switched to its low level as well, the pixel driving electrode PE is brought into a floating condition, so that the liquid crystal capacity is retained with a driving voltage for negative polarity.
Thereafter, by repeating the operation of intermittently activating the transistor Q7 with use of the load characteristics control signal of the line B in synchronism with the switching operation to turn of the above switching transistors Q5 and Q6 alternately, the pixel electrode PE of the liquid crystal element LC is impressed with a driving voltage VPE alternated in current by respective video signals with positive-polarity and negative-polarity, as shown in FIG. 2E. In this way, as the pixel 10 is adapted so as to not transfer the retained electrical charge to the pixel electrode PE directly but supply the voltages through the source follower buffers, there arises no problem of electrical charges being neutralized in spite of charging and discharging at positive and negative polarities repeatedly, allowing the driving operation to be realized with no attenuation in its voltage level.
In FIG. 2F, Vcom designates a voltage to be applied to the common electrode CE formed on the opposed substrate of the liquid crystal display device. A substantial AC driving voltage of the liquid crystal layer LCM is equal to a differential voltage between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel electrode PE. As shown in FIG. 2F, the applied voltage Vcom of the common electrode CE is inversed in synchronism with the switching of pixel polarity for a reference level generally equal to the inversion reference level Vc of the potential of the pixel electrode. Consequently, the absolute values of potentials difference between the applied voltage Vcom to the common electrode CE and the applied voltages (of both polarities) to the pixel driving electrode PE always become equal to each other, so that the liquid crystal layer LCM is impressed with alternating-current voltages VLC having no direct-current component, as shown in FIG. 2G In the pixel 10, therefore, by switching the voltage applied to the common electrode CE in reverse phases against the pixel electrode PE, it is possible to reduce the amplitude of voltages supplied to the pixel electrode PE, whereby the withstand voltages of respective transistors on the side of the drive circuit and its power consumption can be saved.
Again, the video signal voltages sampled and retained in the retentive capacities Cs1 and Cs2 are read out by the transistors Q3 and Q4 forming the source follower circuits having high input resistances. Then, the so-readout voltages are alternately selected by the switching transistors Q5 and Q6 that are activated by the gate control signals alternately supplied to the lines S+, S−, as shown in FIGS. 2C and 2D. Successively, the so-selected voltages are applied to the pixel electrode PE, in the form of the drive voltage VPE inverting its polarity (between positive polarity and negative polarity) shown in FIG. 2E. In the pixel 10 of FIG. 1, once respective (positive and negative) video signal voltages are written in the retentive capacities Cs1 and Cs2 during one vertical scanning period (i.e. one frame), the video signal voltages could be selected from the retentive capacities Cs1 and Cs2 to drive the liquid crystal element LC in AC (alternating current) due to alternate switching of the transistors Q5 and Q6, within one frame as many times as one wants until the video signal voltages of the next frame are retained. Thus, the pixel 10 is capable of AC-driving the liquid crystal element LC at a high frequency with no restriction from a vertical scanning frequency, independently of a writing period of video signals.
Irrespective of the vertical scanning frequency, this AC drive frequency can be established by an inversion control period at a pixel circuit freely. Assume that, for instance, the vertical scanning frequency is equal to 60 Hz in general TV video signals, and the liquid display device is constructed by 1125 lines of Full Hi-Vision in the number of vertical-period scanning lines. If the polarity switching of a pixel circuit is performed with a period of about 15 lines, then the AC driving frequency of the liquid crystal element becomes 2.25 kHz (=60 (Hz)×1125/(15×2)), allowing the liquid crystal driving frequency to be enhanced in comparison with the conventional liquid crystal display device dramatically. As a result, it is possible to avoid a phenomenon of burn-in in comparison with a situation where the AC drive frequency of the liquid crystal element is low and also possible to remarkably improve device's reliability/stability while avoiding deterioration (spots etc.) of displaying quality.